1. Field of the Invention
The present invention relates to digital circuits, and more particularly to a digital circuit which includes a delay circuit, such as a flip-flop circuit, and a logical circuit.
2. Description of the Prior Art
Digital circuits each including a delay circuit and a logical circuit have hitherto been known. An example of the digital circuits having been generally employed is shown in FIG. 1a.
In the figure, L.sub.1 designates a logical circuit, to which an input signal I.sub.1 is fed from a circuit, for example, a logical circuit at the preceding stage. D.sub.1 indicates a delay circuit, which is, by way of example, a dynamic flip-flop circuit of 1 bit composed of field-effect transistors. The flip-flop circuit comprises field-effect transistors Tt.sub.1 and Tt.sub.2 for transfer gates which are delay means, field-effect transistors Tl.sub.1 and Tl.sub.2 which function as load resistances, and field-effect transistors Td.sub.1 and Td.sub.2 which serve to temporarily store information. The transistors Td.sub.1 and Tl.sub.1, and those Td.sub.2 and Tl.sub.2 constitute inverter circuits, respectively. The gate electrodes of the transistors Tt.sub.1 and Tt.sub.2 have clock pulses .phi..sub.1 and .phi..sub.2 applied thereto, respectively, the clock pulses differing in phase from each other as shown in FIG. 1c.
Herein, if a delay of the input signal I.sub.1 and a delay of the logical circuit L.sub.1 do not occur, there is no problem. In contrast, a problem occurs where the phase difference Tpl between the clock pulses .phi..sub.1 and .phi..sub.2 is exceeded as shown in FIG. 1c by the sum (Tdi + Tdl) between the delay Tdi of the input signal I.sub.1 with respect to the clock pulse .phi..sub.2, the delay resulting from the input signal being fed to the logical circuit L.sub.1 via another logical circuit, a buffer circuit or the like, being connected at the stage previous to the logical circuit L.sub.1, and the delay Tdl of the signal as is caused in the logical circuit L.sub.1.
More specifically, the output signal Va of the logical circuit L.sub.1 should originally be written in the storage transistor Td.sub.1 by the transistor Tt.sub.1 at the time of a trigger portion X of the clock pulse train .phi..sub.1. Nevertheless, it is written at the time of the next trigger portion Y because of the delay (Tdi + Tdl) discussed above. As a result, while the delay Tda of an output signal O.sub.1 a with respect to the clock pulse .phi..sub.2 should be one period T (1 bit) of the clock pulse train .phi..sub.2, it becomes a delay corresponding to 2 bits as is illustrated in FIG. 1c.
On the other hand, the connection relation between the logical circuit L.sub.1 and the delay circuit D.sub.1 may be reversed in order to make the delay Tdi of the input signal I.sub.1 negligible. In this case, however, it is inevitable that the delay Tdl of the logical circuit L.sub.1 is added to the output signal.